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This version:
Feb. 23. 1999
Semiconductor MSC23140D-xxBS10/DS10
1,048,576-word x 40-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE
DESCRIPTION
The MSC23140D-xxBS10/DS10 is a fully decoded, 1,048,576-word x 40-bit CMOS dynamic random access memory module composed of ten 4Mb DRAMs in SOJ packages mounted with ten decoupling capacitors on a 72pin glass epoxy single-inline package. This module supports any application where high density and large capacity of storage memory are required.
FEATURES
* 1,048,576-word x 40-bit organization * 72-pin socket insertable module MSC23140D-xxBS10 : Gold tab MSC23140D-XXDS10 : Solder tab * Single +5V supply 10% tolerance * Input : TTL compatible * Output : TTL compatible, 3-state * Refresh : 1024cycles/16ms * /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability * Fast page mode capability * Multi-bit test mode capability
PRODUCT FAMILY
Access Time (Max.) Family tRAC MSC23140D-60BS10/DS10 MSC23140D-70BS10/DS10 60ns 70ns tAA 30ns 35ns tCAC 15ns 20ns tOEA 15ns 20ns
Cycle Time (Min.) Operating(Max.) Standby(Max.)
Power Dissipation
110ns 130ns
4950mW 55mW 4400mW
Semiconductor
MSC23140D
MODULE OUTLINE
MSC23140D-xxBS10/DS10
107.950.2*1 101.19Typ. (Unit : mm) 5.28Max.
3.38Typ.
3.18
25.40.2 Typ. Typ. 10.16 6.35 2.03Typ. 6.35Typ. 3.5Min. +0.1 1.27 -0.08
1 1.270.1 R1.57 6.35 95.25 1.04Typ.
72
*1 The common size difference of the board width 12.5mm of its height is specified as 0.2. The value above 12.5mm is specified as 0.5.
Semiconductor
MSC23140D
PIN CONFIGURATION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin Name VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC NC A0 A1 A2 A3 A4 A5 A6 Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name /OE DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A7 DQ16 VCC A8 A9 NC NC DQ17 DQ18 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pin Name DQ19 DQ20 VSS /CAS0 NC NC NC /RAS0 NC DQ21 /WE VSS DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 PD1 PD2 PD3 PD4 DQ39 VSS
Presence Detect Pins
MSC23140D -60BS10/DS10 VSS VSS NC NC MSC23140D -70BS10/DS10 VSS VSS VSS NC
Pin No. 67 68 69 70
Pin Name PD1 PD2 PD3 PD4
Semiconductor
MSC23140D
BLOCK DIAGRAM
A0-A9 /RAS0 /CAS0 /WE /OE A0-A9 /RAS /CAS /WE /OE VCC DQ DQ DQ DQ VSS DQ0 DQ1 DQ2 DQ3 A0-A9 /RAS /CAS /WE /OE VCC DQ DQ DQ DQ VSS DQ20 DQ21 DQ22 DQ23
A0-A9 /RAS /CAS /WE /OE VCC A0-A9 /RAS /CAS /WE /OE VCC
DQ DQ DQ DQ VSS DQ DQ DQ DQ VSS
DQ4 DQ5 DQ6 DQ7
A0-A9 /RAS /CAS /WE /OE VCC A0-A9 /RAS /CAS /WE /OE VCC
DQ DQ DQ DQ VSS DQ DQ DQ DQ VSS
DQ24 DQ25 DQ26 DQ27
DQ8 DQ9 DQ10 DQ11
DQ28 DQ29 DQ30 DQ31
A0-A9 /RAS /CAS /WE /OE VCC
DQ DQ DQ DQ VSS
DQ12 DQ13 DQ14 DQ15
A0-A9 /RAS /CAS /WE /OE VCC
DQ DQ DQ DQ VSS
DQ32 DQ33 DQ34 DQ35
A0-A9 /RAS /CAS /WE /OE VCC
DQ DQ DQ DQ VSS
DQ16 DQ17 DQ18 DQ19
A0-A9 /RAS /CAS /WE /OE VCC
DQ DQ DQ DQ VSS
DQ36 DQ37 DQ38 DQ39
VCC VSS C1-C10
Semiconductor
MSC23140D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
( Ta = 25C ) Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD TOPR TSTG Rating -1.0 to +7.0 -1.0 to +7.0 50 10 0 to +70 -40 to +125 Unit V V mA W C C
Recommended Operating Conditions
( Ta = 0C to +70C ) Parameter Power Supply Voltage VSS Input High Voltage Input Low Voltage VIH VIL 0 2.4 -1.0 0 0 6.5 0.8 V V V Symbol VCC Min. 4.5 Typ. 5.0 Max. 5.5 Unit V
Capacitance
( VCC = 5V 10%, Ta = 25C, f = 1 MHz ) Parameter Input Capacitance (A0 - A9) Input Capacitance (/RAS0, /CAS0, /WE, /OE) I/O Capacitance (DQ0 - DQ39) Symbol CIN1 CIN2 CDQ Typ. Max. 70 80 13 Unit pF pF pF
Note:
Capacitance measured with Boonton Meter.
Semiconductor
MSC23140D
DC Characteristics
(VCC = 5V 10%, Ta = 0C to +70C ) Symbo l MSC23140D -60BS10/DS10 Min. Input Leakage Current ILI 0V VIN 6.5V: All other pins not under test = 0V Data out is disable 0V VOUT 5.5V IOH = -5.0mA IOL = 4.2mA /RAS cycling, /CAS cycling, tRC = min. /RAS = VIH /CAS = VIH /RAS cycling, /CAS = VIH, tRC = min. tRC = min. /RAS = VIL, /CAS cycling, tPC = min. TTL MOS -100 Max. 100 MSC23140D -70BS10/DS10 Min. -100 Max. 100 A
Parameter
Condition
Unit
Note
Output Leakage Current Output High Voltage Output Low Voltage Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (/RAS only refresh) Average Power Supply Current (/CAS before /RAS refresh) Average Power Supply Current (Fast Page Mode)
ILO VOH VOL ICC1
-10 2.4 0 -
10 VCC 0.4 900 20 10 900
-10 2.4 0 -
10 VCC 0.4 800 20 10 800
A V V mA mA mA mA 1, 2 1 1 1, 2
ICC2
ICC3
ICC6
-
900
-
800
mA
1, 2
ICC7
-
700
-
600
mA
1, 3
Notes: 1. ICC is dependent on output loading and cycles rates. Specified values are obtained with the output open. 2. Address can be changed once or less while /RAS = VIL. 3. Address can be changed once or less while /CAS = VIH.
Semiconductor
MSC23140D
AC Characteristics (1/2)
(VCC = 5V 10%, Ta = 0C to +70C ) Note: 1, 2, 3, 11, 12 Parameter Symbol MSC23140D -60BS10/DS10 Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from /RAS Access Time from /CAS Access Time from Column Address Access Time from /CAS Precharge Access Time from /OE Output Low Impedance Time from /CAS /CAS to Data Output Buffer Turn-off Delay Time /OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period /RAS Precharge Time /RAS Pulse Width /RAS Pulse Width (Fast Page Mode) /RAS Hold Time /RAS Hold Time referenced to /OE /CAS Precharge Time (Fast Page Mode) /CAS Pulse Width /CAS Hold Time /CAS to /RAS Precharge Time /RAS Hold Time from /CAS Precharge /RAS to /CAS Delay Time /RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from /RAS Column Address to /RAS Lead Time tRC tRWC tPC t PRWC tRAC tCAC tAA t CPA tOEA tCLZ tOFF tOEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tAR t RAL 110 150 40 80 0 0 0 3 40 60 60 15 15 10 15 60 5 35 20 15 0 10 0 15 50 30 Max. 60 15 30 35 15 15 15 50 16 10K 100K 10K 45 30 MSC23140D -70BS10/DS10 Min. 130 180 45 95 0 0 0 3 50 70 70 20 20 10 20 70 5 40 20 15 0 10 0 15 55 35 Max. 70 20 35 40 20 20 20 50 16 10K 100K 10K 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 4, 5, 6 4, 5 4, 6 4 4 4 7 7 3 Unit Note
Semiconductor
MSC23140D
AC Characteristics (2/2)
(VCC = 5V 10%, Ta = 0C to +70C ) Note: 1, 2, 3, 11, 12 Parameter Symbol MSC23140D -60BS10/DS10 Min. Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to /RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from /RAS Write Command Pulse Width /OE Command Hold Time Write Command to /RAS Lead Time Write Command to /CAS Lead time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from /RAS /OE to Data-in Delay Time /CAS to /WE Delay Time Column Address to /WE Delay Time /RAS to /WE Delay Time /CAS Precharge /WE Delay Time /CAS Active Delay Time from /RAS Precharge /RAS to /CAS Set-up Time (/CAS before /RAS) /RAS to /CAS Hold Time (/CAS before /RAS) /WE to /RAS Precharge Time (/CAS before /RAS) /WE Hold Time from /RAS (/CAS before /RAS) /RAS to /WE Set-up Time (Test Mode) /RAS to /WE Hold Time (Test Mode) tRCS tRCH tRRH tWCS tWCH tWCR tWP tOEH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH 0 0 0 0 10 45 10 15 15 15 0 15 50 15 35 50 80 55 10 5 10 10 10 10 10 Max. MSC23140D -70BS10/DS10 Min. 0 0 0 0 10 50 10 20 20 20 0 15 55 20 45 60 95 65 10 5 10 10 10 10 10 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 10 10 8 8 9 Unit Note
Semiconductor
MSC23140D
Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assumes tT = 5ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tOFF(Max.) and tOEZ(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(Min.), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD(Min.), tRWD tRWD(Min.), tAWD tAWD(Min.) and tCPWD tCPWD(Min.), the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither or the above sets of conditions is satisfied, the conditions of the data out (at access time) is indeterminate. 10. These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading edge in an /OE control write cycle or a read modify write cycle. 11. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA0 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by a /RAS only refresh or /CAS before /RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.

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